LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1097

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
CAN message interface message control registers
Table 1032.CAN message interface message control registers (IF1_MCTRL, address
Bit
3:0
6:4
7
8
9
10
11
12
Symbol
DLC[3:0]
-
EOB
TXRQST
RMTEN
RXIE
TXIE
UMASK
0x400E 2038 and IF2_MCTRL, address 0x400E 2098) bit description
All information provided in this document is subject to legal disclaimers.
Value
1
0
1
0
1
0
1
0
1
0
1
0
Rev. 00.13 — 20 July 2011
Description
Data length code
Remark: The Data Length Code of a Message
Object must be defined the same as in all the
corresponding objects with the same identifier at
other nodes. When the Message Handler stores
a data frame, it will write the DLC to the value
given by the received message.
0000 to 1000 = Data frame has 0 - 8 data bytes.
1001 to 1111 = Data frame has 8 data bytes.
reserved
End of buffer
Single message object or last message object of
a FIFO buffer.
Message object belongs to a FIFO buffer and is
not the last message object of that FIFO buffer.
Transmit request
The transmission of this message object is
requested and is not yet done
This message object is not waiting for
transmission.
Remote enable
At the reception of a remote frame, TXRQST is
set.
At the reception of a remote frame, TXRQST is
left unchanged.
Receive interrupt enable
INTPND will be set after successful reception of
a frame.
INTPND will be left unchanged after successful
reception of a frame.
Transmit interrupt enable
INTPND will be set after a successful reception
of a frame.
The INTPND bit will be left unchanged after a
successful reception of a frame.
Use acceptance mask
Remark: If UMASK is set to 1, the message
object’s mask bits have to be programmed
during initialization of the message object before
MAGVAL is set to 1.
Use mask (MSK[28:0], MXTD, and MDIR) for
acceptance filtering.
Mask ignored.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0000
-
0
0
0
0
0
0
1097 of 1164
Access
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W