LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 331

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.5 Dynamic Memory Refresh Timer register
19.7.6 Dynamic Memory Read Configuration register
The DynamicRefresh register configures dynamic memory operation. It is recommended
that this register is modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. However, these control bits can, if necessary, be
altered during normal operation. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 270. Dynamic Memory Refresh Timer register (DYNAMICREFRESH - address
For example, for the refresh period of 16 µs, and a CCLK frequency of 50 MHz, the
following value must be programmed into this register:
(16 x 10
If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),
the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the
clock rate is reduced during the wake-up period of a reset cycle. During this period, the
EMC (and all other portions of the chip that are being clocked) run from the IRC oscillator
at 12 MHz. The IRC oscillator frequency must be used as the CCLK rate for refresh
calculations if auto-refresh through warm reset is requested.
Note: The refresh cycles are evenly distributed. However, there might be slight variations
when the auto-refresh command is issued depending on the status of the memory
controller.
The DynamicReadConfig register configures the dynamic memory read strategy. This
register must only be modified during system initialization. This register is accessed with
one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Important: It should be highlighted that the default clock delay methodology requires the
output clock to be delayed externally to the chip to avoid hold time issue for the SDRAM.
In most application boards, there will be no such external delay circuit and the application
should write correct value to the DynamicReadConfig register to use Command Delay
Strategy. The Clock Delay Strategy is the default setting on reset!
Bit
10:0
31:11 -
Symbol
REFRESH Refresh timer.
-6
x 50 x 10
0x4000 5024) bit description
All information provided in this document is subject to legal disclaimers.
6
Description
Indicates the multiple of 16 CCLKs between SDRAM refresh cycles.
0x0 = Refresh disabled (POR reset value).
0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles.
For example:
0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles.
0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
) / 16 = 50 or 0x32
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
-