LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 731

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.14 UART Smart card interface control register
After reset the USART will be in full-duplex mode, meaning that both TX and RX work
independently. After setting the HDEN bit, the USART will be in half-duplex mode. In this
mode, the USART ensures that the receiver is locked when idle, or will enter a locked
state after having received a complete ongoing character reception. Line conflicts must be
handled in software. The behavior of the USART is unpredictactable when data is
presented for reception while data is being transmitted.
For this reason, the value of the HDEN register should not be modified while sending or
receiving data, or data may be lost or corrupted.
Table 680. UART Half duplex enable register (HDEN - addresses 0x4008 1040 (UART0),
Table 681. UART Smart card interface control register (SCICTRL - addresses 0x4008 1048
Bit
0
31:1
Bit
0
1
2
7:5
15:8
31:16
Symbol
HDEN
-
Symbol
SCIEN
NACKDIS
PROTSEL
TXRETRY
GUARDTIME
-
0x400C 1040 (UART2), 0x400C 2040 (UART3)) bit description
(UART0), 0x400C 1048 (UART2), 0x400C 2048 (UART3)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value Description
0
1
Value Description
0
1
0
1
0
1
-
Half-duplex mode enable
Disable half-duplex mode.
Enable half-duplex mode.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Smart Card Interface Enable.
Smart card interface disabled.
Asynchronous half duplex smart card interface is
enabled.
NACK response disable. Only applicable in T=0.
A NACK response is enabled.
A NACK response is inhibited.
Protocol selection as defined in the ISO7816-3 standard. 0
T = 0
T = 1
Maximum number of retransmissions in case of a
negative acknowledge (protocol T=0). When the retry
counter is exceeded, the USART will be locked until the
FIFO is cleared. A TX error interrupt is generated when
enabled.
standard guard time as defined in ISO 7816-3,
depending on the protocol type. A guard time of 0xFF
indicates a minimal guard time as defined for the
selected protocol.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Extra guard time. No extra guard time (0x0) results in a
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
-
Reset
value
0
0
-
NA