LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 360

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.6.2 Device/host capability registers
The following registers and register bits are used for OTG operations. The values of these
register bits are independent of the controller mode and are not affected by a write to the
RESET bit in the USBCMD register.
Table 301. CAPLENGTH register (CAPLENGTH - address 0x4000 6100) bit description
Bit
7:0
23:8
31:24
Fig 36. USB controller modes
•
•
•
•
All identification registers
All device/host capabilities registers
All bits of the OTGSC register
The following bits of the PORTSC register
– PTS (parallel interface select)
– STS (serial transceiver select)
– PTW (parallel transceiver width)
– PHCD (PHY low power suspend)
– WKOC, WKDC, WKCN (wake signals)
– PIC[1:0] (port indicators)
– PP (port power)
Symbol
CAPLENGTH
HCIVERSION
-
USBCMD RST bit = 1
Hardware reset or
All information provided in this document is subject to legal disclaimers.
write 10 to USBMODE
Rev. 00.13 — 20 July 2011
MODE = 10
DEVICE
Description
Indicates offset to add to the register base
address at the beginning of the Operational
Register
BCD encoding of the EHCI revision number
supported by this host controller.
These bits are reserved and should be set to
zero.
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
(Section
MODE = 00
20.6.16)
IDLE
(Section
20.6.15):
MODE = 11
write 11 to USBMODE
HOST
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x40
0x100
-
360 of 1164
Access
RO
RO
-