LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 422

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.8.1.1 Setup Packet Handling using setup lockout mechanism
20.10.8.1.2 Setup Packet Handling using trip wire mechanism
The setup lockout will engage so that future setup packets are ignored. Lockout of setup
packets ensures that while software is reading the setup packet stored in the queue head,
that data is not written as it is being read potentially causing an invalid setup packet.
In hardware the setup lockout mechanism can be disabled and a new tripwire type
semaphore will ensure that the setup packet payload is extracted from the queue head
without being corrupted by an incoming setup packet. This is the preferred behavior
because ignoring repeated setup packets due to long software interrupt latency would be
a compliance issue.
After receiving an interrupt and inspecting USBMODE to determine that a setup packet
was received on a particular pipe:
Remark: To limit the exposure of setup packets to the setup lockout mechanism (if used),
the DCD should designate the priority of responding to setup packets above responding to
other packet completions
1. Duplicate contents of dQH.SsetupBuffer into local software byte array.
2. Write '1' to clear corresponding ENDPTSETUPSTAT bit and thereby disabling Setup
3. Process setup packet using local software byte array copy and execute
4. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is ‘0’.
•
•
Lockout (i.e. the Setup Lockout activates as soon as a setup arrives. By writing to the
ENDPTSETUPSTAT, the device controller will accept new setup packets.).
status/handshake phases.
Remark: After receiving a new setup packet the status and/or handshake phases
may still be pending from a previous control sequence. These should be flushed &
deallocated before linking a new status and/or handshake dTD for the most recent
setup packet.
The time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ may vary
according to the type of traffic on the bus up to nearly a 1ms, however the it is
absolutely necessary to ensure ENDPTSETUPSTAT has transitioned to ‘0’ after step
1) and before priming for the status/handshake phases.
Disable Setup Lockout by writing ‘1’ to Setup Lockout Mode (SLOM) in USBMODE.
(once at initialization). Setup lockout is not necessary when using the tripwire as
described below.
Remark: Leaving the Setup Lockout Mode As ‘0’ will result in pre-2.3 hardware
behavior.
After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a
setup packet was received on a particular pipe:
a. Write '1' to clear corresponding bit ENDPTSETUPSTAT.
b. Duplicate contents of dQH.SetupBuffer into local software byte array.
c. Write ‘1’ to Setup Tripwire (SUTW) in USBCMD register.
d. Read Setup TripWire (SUTW) in USBCMD register. (if set - continue; if cleared - go
e. Write '0' to clear Setup Tripwire (SUTW) in USBCMD register.
to b).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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