LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 133

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
11.4.4.6 Reset external status registers for PERIPHERAL_RESET
11.4.4.7 Reset external status registers for MASTER_RESET
Refer to
source.
Table 105. Reset external status registers x (RESET_EXT_STATx, address 0x4005 34xx) bit
Refer to
source. These are the ARM Cortex-M3 core, the LCD controller, the USB0, the GPDMA,
the SDIO controller, the external memory controller, the Ethernet controller, and the AES.
The reset value is dependent on the peripheral, see
Table 106. Reset external status registers y (RESET_EXT_STATy, address 0x4005 34yy) bit
Bit
1:0
2
31:3
Bit
2:0
3
31:4
-
-
Symbol
PERIPHERAL_RESET Reset activated by PERIPHERAL_RST
-
Symbol
MASTER_RESET
-
Table 91
Table 91
description
description
All information provided in this document is subject to legal disclaimers.
for reset generators which have the PERIPH_RST output as reset
for reset generators which have the MASTER_RST output as reset
Rev. 00.13 — 20 July 2011
Description
Reserved. Do not modify; read as logic 0.
output. Write 0 to clear.
0 = Reset not activated
1 = Reset activated
Reserved. Do not modify; read as logic 0.
Description
Reserved. Do not modify; read as logic 0.
Reset activated by MASTER_RST output.
Write 0 to clear.
0 = Reset not activated
1 = Reset activated
Reserved. Do not modify; read as logic 0.
Chapter 11: LPC18xx Reset Generation Unit (RGU)
Table
91.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
Reset
value
0
0
0
133 of 1164
Access
-
R/W
-
Access
-
R/W
-