LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 693

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
30.6 Clocking
30.7 Register description
<Document ID>
User manual
30.7.1 Watchdog mode register
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the BASE_M3_CLK. The WDCLK
is used for the watchdog timer counting and is derived from the IRC. The clock source (the
IRC) is fixed to ensure that the WDT always has a valid clock.
There is some synchronization logic between these two clock domains. When the MOD
and TC registers are updated by APB operations, the new value will take effect in three
WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog timer is
counting the WDCLK clock cycles, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the TV register
by the CPU.
The Watchdog contains six registers as shown in
Table 622. Register overview: Watchdog timer (base address 0x4008 0000)
[1]
The WDMOD register controls the operation of the Watchdog as per the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
Name
MOD
TC
FEED
TV
-
WARNINT
WINDOW
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Access Address
R/W
R/W
WO
RO
-
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
Description
Watchdog mode register. This register
contains the basic mode and status of the
Watchdog Timer.
Watchdog timer constant register. This register
determines the time-out value.
Watchdog feed sequence register. Writing
0xAA followed by 0x55 to this register reloads
the Watchdog timer with the value contained in
WDTC.
Watchdog timer value register. This register
reads out the current value of the Watchdog
timer.
Reserved
Watchdog warning interrupt register. This
register contains the Watchdog warning
interrupt compare value.
Watchdog timer window register. This register
contains the Watchdog window value.
Table 622
below.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0xFF
NA
0xFF
-
0
0xFF FFFF
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[1]