LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 758

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 702: UART1 Modem Status Register (MSR - address 0x4008 2018) bit description
Table 703: UART1 Scratch Pad Register (SCR - address 0x4008 2014) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
31:8
Bit
7:0
31:8
Symbol
DCTS
DDSR
TERI
DDCD
CTS
DSR
RI
DCD
-
Symbol Description
Pad
-
33.5.12 UART1 Scratch Pad Register
33.5.13 UART1 Auto-baud Control Register
Scratch pad. A readable, writable byte.
Reserved, the value read from a reserved bit is not defined.
The U1SCR has no effect on the UART1 operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U1SCR has occurred.
The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Value Description
-
0
1
0
1
0
1
0
1
-
-
-
-
Delta CTS.
Set upon state change of input CTS. Cleared on an U1MSR read.
No change detected on modem input, CTS.
State change detected on modem input, CTS.
Delta DSR.
Set upon state change of input DSR. Cleared on an U1MSR read.
No change detected on modem input, DSR.
State change detected on modem input, DSR.
Trailing Edge RI.
Set upon low to high transition of input RI. Cleared on an U1MSR read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Delta DCD. Set upon state change of input DCD. Cleared on an U1MSR
read.
No change detected on modem input, DCD.
State change detected on modem input, DCD.
Clear To Send State. Complement of input signal CTS. This bit is
connected to U1MCR[1] in modem loopback mode.
Data Set Ready State. Complement of input signal DSR. This bit is
connected to U1MCR[0] in modem loopback mode.
Ring Indicator State. Complement of input RI. This bit is connected to
U1MCR[2] in modem loopback mode.
Data Carrier Detect State. Complement of input DCD. This bit is connected
to U1MCR[3] in modem loopback mode.
Reserved, the value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0
0
0
0
0
0
NA
Reset value
0x00
NA
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