LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 907

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
39.5 Register description
<Document ID>
User manual
39.5.1 D/A converter register
39.5.2 D/A Converter Control register
Table 836. Register overview: DAC (base address 0x400E 1000)
This read/write register includes the digital value to be converted to an analog output
value and a bit that trades off performance vs. power.
Table 837: D/A Converter register (CR - address 0x400E 1000) bit description
This read/write register enables the DMA operation and controls the DMA timer.
Table 838. D/A Control register (CTRL - address 0x400E 1004) bit description
Name
CR
CTRL
CNTVAL
Bit
5:0
15:6
16
31:17 -
Bit
0
1
Symbol
INT_DMA_REQ
DBLBUF_ENA
Symbol Value
-
VALUE
BIAS
All information provided in this document is subject to legal disclaimers.
0
1
R/W
Access
R/W
R/W
Rev. 00.13 — 20 July 2011
Value Description
0
1
0
1
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
After the selected settling time after this field is written with a
new VALUE, the voltage on the DACOUT pin (with respect to
V
Settling time
The settling time of the DAC is 1  s max, and the maximum
current is 700  A.
The settling time of the DAC is 2.5  s and the maximum
current is 350  A.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
SSA
) is VALUE/1024  VDDA.
DMA request
This bit is cleared on any write to the DACR register.
This bit is set by hardware when the timer times out.
DMA double-buffering
DACR double-buffering is disabled.
When this bit and the CNT_ENA bit are both set, the
double-buffering feature in the DACR register will be
enabled. Writes to the DACR register are written to a
pre-buffer and then transferred to the DACR on the next
time-out of the counter.
Address
offset
0x000
0x004
0x008
Description
DAC register. Holds the conversion
data.
DAC control register.
DAC counter value register.
Chapter 39: LPC18xx DAC
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
907 of 1164
Reset
value
-
0
0
-
Reset
value
0
0