LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 600

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 511. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description
<Document ID>
User manual
Bit
1:0
3:2
Symbol
SETCLR0
SETCLR1
24.6.12 SCT bidirectional output control register
24.6.11 SCT output register
Value Description
0x0
0x1
0x2
0x0
0x1
0x2
Table 509. SCT match/capture registers mode register (REGMODE - address 0x4000 004C)
The SCT supports 16 outputs, each of which has a corresponding bit in this register.
Software can write to any of the output registers when both counters are halted to control
the outputs directly. Writing to this register when either counter is stopped or running does
not affect the outputs and results in an bus error.
Software can read this register at any time to sense the state of the outputs.
Table 510. SCT output register (OUTPUT - address 0x4000 0050) bit description
This register specifies (for each output) the impact of the counting direction on the
meaning of set and clear operations on the output (see
Section
Bit
15:0
31:16 REGMOD_H
Bit
15:0
31:16
Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
Set and clear do not depend on any counter.
Set and clear are reversed when counter L or the unified counter is counting down.
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
Set and clear do not depend on any counter.
Set and clear are reversed when counter L or the unified counter is counting down.
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Symbol
REGMOD_L
Symbol
OUT
-
24.6.26).
bit description
All information provided in this document is subject to legal disclaimers.
Description
Writing a 1 to bit n makes the corresponding output HIGH. 0 makes
the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,...,
output 15 = bit 15).
Reserved
Description
Each bit controls one pair of match/capture registers (register 0 =
bit 0, register 1 = bit 1,..., register 15 = bit 15).
0 = registers operate as match registers.
1 = registers operate as capture registers.
Each bit controls one pair of match/capture registers (register 0 =
bit 16, register 1 = bit 17,..., register 15 = bit 31).
0 = registers operate as match registers.
1 = registers operate as capture registers.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
Section 24.6.25
UM10430
© NXP B.V. 2011. All rights reserved.
and
600 of 1164
0
0
Reset
value
Reset
value
0
Reset
value
0
0