LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 593

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 499. Register overview: State Configurable Timer (base address 0x4000 0000)
Table 500. SCT configuration register (CONFIG - address 0x4000 0000) bit description
<Document ID>
User manual
Name
OUTPUTCL13
OUTPUTSET14
OUTPUTCL14
OUTPUTSET15
OUTPUTCL15
Bit
0
2:1
Symbol
UNIFY
CLKMODE
24.6.1 SCT configuration register
Access Address
R/W
R/W
R/W
R/W
R/W
This register configures the overall operation of the SCT and should be written before any
other registers.
Value
0
1
0x0
0x1
0x2
0x3
offset
0x56C
0x570
0x574
0x578
0x57C
Description
SCT operation
The SCT operates as two 16-bit counters named L and H.
The SCT operates as a unified 32-bit counter.
SCT clock mode
The SCT and prescaler(s) are clocked by the bus clock.
The SCT clock is the bus clock, but the prescaler(s) is (are) enabled to count
only when sampling of the input selected by the CKSEL field finds the selected
edge. The minimum pulse width on the clock input is 1 bus clock period. This is
the high-performance sampled-clock mode.
The SCT and prescaler(s) are clocked by the input selected by CKSEL,
synchronized to the bus clock and possibly inverted. The minimum pulse width
on the clock input is 1 bus clock period. This is the low-power sampled-clock
mode.
The SCT and prescaler(s) are clocked by the input edge selected by the
CKSEL field. In this mode the following is true:
Most of the SCT is clocked by the (selected polarity of the) input.
Outputs are switched synchronously to the input clock.
The input clock rate must be at least half the bus clock rate and can be faster
than the bus clock.
All information provided in this document is subject to legal disclaimers.
Description
SCT output 13 clear register
SCT output 14 set register
SCT output 14 clear register
SCT output 15 set register
SCT output 15 clear register
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
593 of 1164
Reset
value
0
00