LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1055

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 980. Register overview: GPIO (register base address: 0x400F 0000)
Name
DIR0
-
MASK0
PIN0
SET0
CLR0
DIR1
-
MASK1
PIN1
SET1
CLR1
DIR2
-
MASK2
PIN2
SET2
CLR2
DIR3
-
MASK3
PIN3
SET3
CLR3
DIR4
All information provided in this document is subject to legal disclaimers.
Access Address
R/W
-
R/W
R/W
R/W
W
R/W
-
R/W
R/W
R/W
W
R/W
-
R/W
R/W
R/W
W
R/W
-
R/W
R/W
R/W
W
R/W
Rev. 00.13 — 20 July 2011
0x010
0x014
0x018
0x030
0x034
0x038
0x050
0x054
0x058
0x070
0x074
0x078
offset
0x000
0x004 to
0x00C
0x01C
0x020
0x024 to
0x02C
0x03C
0x040
0x044 to
0x04C
0x05C
0x060
0x064 to
0x06C
0x07C
0x080
Description
GPIO port 0 direction control register.
Reserved.
GPIO port 0 mask register for port access.
GPIO port 0 pin value register using MASK0.
GPIO port 0 output set register using MASK0.
This register controls the state of output pins. Only
bits enabled by 0 in MASK0 can be altered.
GPIO port 0 output clear register using MASK0.
This register controls the state of output pins. Only
bits enabled by 0 in MASK0 can be altered.
GPIO port 1 direction control register.
Reserved.
GPIO port 1 mask register for port access.
GPIO port 1 pin value register using MASK1.
GPIO port 1 output set register using MASK1.
This register controls the state of output pins. Only
bits enabled by 0 in MASK1 can be altered.
GPIO port 1 output clear register using MASK1.
This register controls the state of output pins. Only
bits enabled by 0 in MASK1 can be altered.
GPIO port 2 direction control register.
Reserved.
GPIO port 2 mask register for port access.
GPIO port 2 pin value register using MASK2.
GPIO port 2 output set register using MASK2.
This register controls the state of output pins. Only
bits enabled by 0 in MASK2 can be altered.
GPIO port 2 output clear register using MASK2.
This register controls the state of output pins. Only
bits enabled by 0 in MASK2 can be altered.
GPIO port 3 direction control register.
Reserved.
GPIO port 3 mask register for port access.
GPIO port 3 pin value register using MASK3.
GPIO port 3 output set register using MASK3.
This register controls the state of output pins. Only
bits enabled by 0 in MASK3 can be altered.
GPIO port 3 output clear register using
FIO3MASK. This register controls the state of
output pins. Only bits enabled by 0 in MASK3 can
be altered.
GPIO port 4 direction control register.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x0
-
0x0
0x0
0x0
0x0
0x0
-
0x0
0x0
0x0
0x0
0x0
-
0x0
0x0
0x0
0x0
0x0
-
0x0
0x0
0x0
0x0
0x0
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