LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 741

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
32.7 Architecture
<Document ID>
User manual
Fig 93. Smart card T = 0 waveform
Clock
TXD
start
bit0
The smart card must be set up with the following considerations:
Thereafter, software should monitor card insertion, handle activation, wait for answer to
reset as described in ISO7816-3.
The architecture of the UART is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART.
The UART receiver block, RX, monitors the serial input line, RXD, for valid input. The
UART RX Shift Register (RSR) accepts valid characters via RXD. After a valid character is
assembled in the RSR, it is passed to the UART RX Buffer Register FIFO to await access
by the CPU or host via the generic host interface.
The UART transmitter block, TX, accepts data written by the CPU or host and buffers the
data in the UART TX Holding Register FIFO (THR). The UART TX Shift Register (TSR)
reads the data stored in the THR and assembles the data to transmit via the serial output
pin, TXD1.
bit1
1. If necessary, bring the UART out of reset and enable clocking to the peripheral.
2. Setup an available UART TXD pin for the bidirectional transfers.
3. Setup the match output or PWM clock source. The default clock requirement for most
4. Configure DLL and DLM for baud rate. It may not be necessary to target a specific
5. Configure LCR for character size and parity (typically 8-bit and even parity).
6. Configure SCICTRL with the desired NACK response, extra guard bits, and protocol
7. Place the GPIO output signals into an inactive state where card power is off, RST is
asynchronous cards is 372 times the bit rate.
standard baud rate but rather to maintain a fraction of the previously mentioned clock
rate. For example if the clock rate is set to 4 MHz the baud rate would be 10753. A
clock rate of 3.5712 MHz would need a baud rate of 9600. An ISO 7816 PPS
exchange may require the baud rate to be changed later.
type.
low, and CLK is low and unchanging.
bit2
bit3
All information provided in this document is subject to legal disclaimers.
bit4
Asynchronous transfer
bit5
Rev. 00.13 — 20 July 2011
bit6
bit7
parity
guard1 guard2
NACK
Chapter 32: LPC18xx USART0_2_3
guard1
extra
guard2
extra
guardn
extra
UM10430
© NXP B.V. 2011. All rights reserved.
start
Next transfer or
First retry
bit0
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