LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 875

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 818. Master Transmitter mode
<Document ID>
User manual
Status
Code
(STAT)
0x08
0x10
0x18
0x20
0x28
0x30
0x38
Status of the I
and hardware
A START condition
has been transmitted.
A Repeated START
condition has been
transmitted.
SLA+W has been
transmitted; ACK has
been received.
SLA+W has been
transmitted; NOT ACK
has been received.
Data byte in DAT has
been transmitted;
ACK has been
received.
Data byte in DAT has
been transmitted;
NOT ACK has been
received.
Arbitration lost in
SLA+R/W or Data
bytes.
2
C-bus
Application software response
To/From DAT
Load SLA+W;
clear STA
Load SLA+W or
Load SLA+R;
Clear STA
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
No DAT action or
No DAT action
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
To CON
STA STO SI
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Chapter 37: LPC18xx I2C-bus interface
Next action taken by I
SLA+W will be transmitted; ACK bit will
be received.
As above.
SLA+R will be transmitted; the I
will be switched to MST/REC mode.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
I
slave will be entered.
A START condition will be transmitted
when the bus becomes free.
2
C-bus will be released; not addressed
UM10430
© NXP B.V. 2011. All rights reserved.
2
C hardware
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