LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 239

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
14.4.22 SCT CTIN_5 capture input multiplexer (CTIN_5_IN)
Table 155. SCT CTIN_4 capture input multiplexer (CTIN_4_IN, address 0x400C 7050) bit
Table 156. SCT CTIN_5 capture input multiplexer (CTIN_5_IN, address 0x400C 7054) bit
Bit
2
3
7:4
31:8
Bit
0
1
2
3
7:4
31:8
Symbol
SYNCH
PULSE
SELECT
-
Symbol
INV
EDGE
SYNCH
PULSE
SELECT
-
description
description
All information provided in this document is subject to legal disclaimers.
Value
1
0
1
0
1
0x0
0x1
0x2
0x3
Value
0
1
0
1
0
1
0
1
0x0
0x1
0x2
Rev. 00.13 — 20 July 2011
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Description
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x4 to 0xF are reserved.
CTIN_4
U0_RXD
TBD - I2S1_RX_MWS1
TBD - I2S1_TX_MWS1
Reserved
Description
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x3 to 0xF are reserved.
CTIN_5
U2_RXD
Reserved
Reserved
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
Reset value
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