LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 773

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
34.6.2 SSP Control Register 1
Table 716: SSP Control Register 0 (CR0 - address 0x4008 3000 (SSP0), 0x400C 5000 (SSP1))
This register controls certain aspects of the operation of the SSP controller.
Bit
3:0
5:4
6
7
15:8
31:16 -
Symbol Value Description
DSS
FRF
CPOL
CPHA
SCR
bit description
All information provided in this document is subject to legal disclaimers.
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x0
0x1
0x2
0x3
0
1
0
1
Rev. 00.13 — 20 July 2011
Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are not supported
and should not be used.
4-bit transfer
5-bit transfer
6-bit transfer
7-bit transfer
8-bit transfer
9-bit transfer
10-bit transfer
11-bit transfer
12-bit transfer
13-bit transfer
14-bit transfer
15-bit transfer
16-bit transfer
Frame Format.
SPI
TI
Microwire
This combination is not supported and should not be used.
Clock Out Polarity. This bit is only used in SPI mode.
SSP controller maintains the bus clock low between frames.
SSP controller maintains the bus clock high between frames.
Clock Out Phase. This bit is only used in SPI mode.
SSP controller captures serial data on the first clock transition of
the frame, that is, the transition away from the inter-frame state
of the clock line.
SSP controller captures serial data on the second clock transition
of the frame, that is, the transition back to the inter-frame state of
the clock line.
Serial Clock Rate. The number of prescaler-output clocks per bit
on the bus, minus one. Given that CPSDVSR is the prescale
divider, and the APB clock PCLK clocks the prescaler, the bit
frequency is PCLK / (CPSDVSR  [SCR+1]).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 34: LPC18xx SSP0/1
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0000
00
0
0x00
NA
0