LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 64

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
8.3 Register description
<Document ID>
User manual
8.3.1 Hardware sleep event enable register PD0_SLEEP0_HW_ENA
8.3.2 Sleep power mode register PD0_SLEEP0_MODE
Table 39.
Table 40.
The PD0_SLEEP0_MODE register controls which of the three reduced power modes,
Deep-sleep, Power-down, or Deep power-down is entered when an ARM WFE/WFI
instruction is issued and the SLEEPDEEP bit is set to 1.
Remark: Only the three values listed in
PD0_SLEEP0_MODE register.
Table 41.
Name
PD0_SLEEP0_HW_ENA
-
PD0_SLEEP0_MODE
Bit
0
31:1
Bit
31:0
Symbol
ENA_EVENT0
-
Symbol
PWR_STATE
Register overview: Power Mode Controller (PMC) (base address 0x4004 2000)
Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address
0x4004 2000) bit description
Sleep power mode register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description
All information provided in this document is subject to legal disclaimers.
Description
Selects between Deep-sleep, Power-down, and
Deep power-down modes.
Only one of the following three values can be
programmed in this register:
0x003F 00AA = Deep-sleep mode
0x003F FCBA = Power-down mode
0x003F FF7F = Deep power-down mode
Rev. 00.13 — 20 July 2011
Description
Writing a 1 enables any sleep modes for Cortex-M3.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Access Address
R/W
-
R/W
Chapter 8: LPC18xx Power Management Controller (PMC)
offset
0x000
0x004 -
0x018
0x01C
Table 41
Description
Hardware sleep event enable
register
Reserved
Sleep power mode register
are allowed settings for the
UM10430
Reset
value
© NXP B.V. 2011. All rights reserved.
Reset
value
1
-
Reset value
0x0000 0001
-
Access
R/W
Access
R/W
-
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