LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1103

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.10.7.2.1 Software initialization
42.10.7.1 C_CAN controller state after reset
42.10.7.2 C_CAN operating modes
42.10.7 Functional description
Table 1045.CAN clock divider register (CLKDIV, address 0x400E 2180) bit description
After a hardware reset, the registers hold the values described in
the busoff state is reset and the output CAN_TXD is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
The software initialization is started by setting the bit INIT in the CAN Control Register,
either by software or by a hardware reset, or by entering the busoff state.
During software initialization (INIT bit is set), the following conditions are present:
To initialize the CAN controller, software has to set up the bit timing register and each
message object. If a message object is not needed, it is sufficient to set its MSGVAL bit to
not valid. Otherwise, the whole message object has to be initialized.
Bit
3:0
31:4
•
•
•
•
•
All message transfer from and to the CAN bus is stopped.
The status of the CAN output CAN_TXD is recessive (HIGH).
The EML counters are unchanged.
The configuration registers are unchanged.
Access to the bit timing register and the BRP extension register is enabled if the CCE
bit in the CAN control register is also set.
Symbol
CLKDIVVAL Clock divider value
-
All information provided in this document is subject to legal disclaimers.
Description
CAN_CLK = PCLK/(2
0000: CAN_CLK = PCLK divided by 1.
0001: CAN_CLK = PCLK divided by 2.
0010: CAN_CLK = PCLK divided by 3.
0010: CAN_CLK = PCLK divided by 4.
0011: CAN_CLK = PCLK divided by 5.
0100: CAN_CLK = PCLK divided by 9.
0101: CAN_CLK = PCLK divided by 17.
...
1111: CAN_CLK = PCLK divided by 16385.
reserved
Rev. 00.13 — 20 July 2011
CLKDIVVAL -1
+1)
Table
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
904. Additionally,
Reset
value
0000
-
1103 of 1164
Access
R/W
-