LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 776

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
34.6.7 SSP Raw Interrupt Status Register
34.6.8 SSP Masked Interrupt Status Register
Table 721: SSP Interrupt Mask Set/Clear register (IMSC - address 0x4008 3014 (SSP0),
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPnIMSC.
Table 722: SSP Raw Interrupt Status register (RIS - address 0x4008 3018 (SSP0), RIS -
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.
Bit
0
1
2
3
31:4
Bit
0
1
2
3
31:4
Symbol Description
RORIM
RTIM
RXIM
TXIM
-
Symbol
RORRIS This bit is 1 if another frame was completely received while the RxFIFO
RTRIS
RXRIS
TXRIS
-
0x400C 5014 (SSP1)) bit description
0x400C 5018 (SSP1)) bit description
All information provided in this document is subject to legal disclaimers.
Software should set this bit to enable interrupt when a Receive Overrun
occurs, that is, when the Rx FIFO is full and another frame is completely
received. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
Software should set this bit to enable interrupt when a Receive Time-out
condition occurs. A Receive Time-out occurs when the Rx FIFO is not
empty, and no has not been read for a time-out period. The time-out
period is the same for master and slave modes and is determined by the
SSP bit rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]).
Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
was full. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
This bit is 1 if the Rx FIFO is not empty, and has not been read for a
time-out period. The time-out period is the same for master and slave
modes and is determined by the SSP bit rate: 32 bits at PCLK /
(CPSDVSR  [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full.
This bit is 1 if the Tx FIFO is at least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 34: LPC18xx SSP0/1
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
NA
Reset
value
0
0
1
NA
0