LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 494

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 419. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
7:6
8
Symbol
TSENA
TSCFUP
DT
TSINIT
TSUPDT Time Stamp Update
TSTRIG
TSADDR
EG
-
TSENAL
L
22.6.16 MAC IEEE1588 time stamp control register
Description
Time Stamp Enable
When this bit, is set the timestamping is enabled for transmit and receive frames.
When disabled timestamp is not added for transmit and receive frames and the
TimeStamp Generator is also suspended. User has to always initialize the TimeStamp
(system time) after enabling this mode.
Time Stamp Fine or Coarse Update
When set, indicates that the system times update to be done using fine update
method. When reset it indicates the system time stamp update to be done using
Coarse method. This bit is reserved if the fine correction option is not enabled.
Time Stamp Initialize
When set, the system time is initialized (over-written) with the value specified in the
Time Stamp High Update and Time Stamp Low Update registers. This register bit
should be read zero before updating it. This bit is reset once the initialize is complete.
When set, the system time is updated (added/subtracted) with the value specified in
the Time Stamp High Update and Time Stamp Low Update registers. This register bit
should be read zero before updating it. This bit is reset once the update is completed
in hardware.
Time Stamp Interrupt Trigger Enable
When set, the Time Stamp interrupt is generated when the System Time becomes
greater than the value written in Target Time register. This bit is reset after the
generation of Time Stamp Trigger Interrupt.
Addend Reg Update
When set, the contents of the Time Stamp Addend register is updated in the PTP
block for fine correction. This is cleared when the update is completed. This register
bit should be zero before setting it. This is a reserved bit when only coarse correction
option is selected.
Reserved
Enable Time Stamp for All Frames
When set, the time stamp snapshot is enabled for all frames received by the core.
Table 418. MAC Address 0 low register (MAC_ADDR0_LOW, address 0x4001 0044) bit
This register controls the operation of the System Time generator and the snooping of
PTP packets for time-stamping in the Receiver.
Bit
31:0
Symbol
A31_0
description
All information provided in this document is subject to legal disclaimers.
Description
MAC Address0 [31:0]
This field contains the lower 32 bits of the 6-byte first
MAC address. This is used by the MAC for filtering for
received frames and for inserting the MAC address in
the Transmit Flow Control (PAUSE) Frames.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
Reset
value
0xFFFF
FFFF
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
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Access
R/W
R/W
R/W/S
C
R/W/S
C
R/WSC
R/W
Access
R/W