LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 562

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.24 Cursor Raw Interrupt Status register
23.6.25 Cursor Masked Interrupt Status register
Table 478. Cursor Interrupt Clear register (CRSR_INTCLR, address 0x4000 8C24) bit
The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the
CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt
controller.
The contents of the CRSR_INTRAW register are described in
Table 479. Cursor Raw Interrupt Status register (CRSR_INTRAW, address 0x4000 8C28) bit
The CRSR_INTSTAT register is set to indicate a cursor interrupt providing that the
interrupt is not masked in the CRSR_INTMSK register.
The contents of the CRSR_INTSTAT register are described in
Table 480. Cursor Masked Interrupt Status register (CRSR_INTSTAT, address 0x4000 8C2C)
Bits
0
31:1
Bits
0
31:1
Bits
0
31:1
Function
CRSRIC
-
Function
CRSRRIS
-
Function
CRSRMIS
-
description
description
bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Cursor interrupt clear.
Writing a 0 to this bit has no effect.
Writing a 1 to this bit causes the cursor interrupt status to be
cleared.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Cursor raw interrupt status.
The cursor interrupt status is set immediately after the last data
is read from the cursor image for the current frame.
This bit is cleared by writing to the CrsrIC bit in the
CRSR_INTCLR register.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Cursor masked interrupt status.
The cursor interrupt status is set immediately after the last data
read from the cursor image for the current frame, providing that
the corresponding bit in the CRSR_INTMSK register is set.
The bit remains clear if the CRSR_INTMSK register is clear.
This bit is cleared by writing to the CRSR_INTCLR register.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 23: LPC18xx LCD
Table
Table
479.
480.
UM10430
© NXP B.V. 2011. All rights reserved.
562 of 1164
Reset
value
0x0
-
Reset
value
0x0
-
Reset
value
0x0
-