LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 430

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.11.5 Flushing/De-priming an endpoint
20.10.11.6 Device error matrix
Should any combination other than the one shown above exist, the DCD must take proper
action. Transfer failure mechanisms are indicated in the Device Error Matrix (see
Table
In addition to checking the status bit, the DCD must read the Transfer Bytes field to
determine the actual bytes transferred. When a transfer is complete, the Total Bytes
transferred is decremented by the actual bytes transferred. For Transmit packets, a
packet is only complete after the actual bytes reaches zero, but for receive packets, the
host may send fewer bytes in the transfer according the USB variable length packet
protocol.
It is necessary for the DCD to flush to de-prime one more endpoints on a USB device
reset or during a broken control transfer. There may also be application specific
requirements to stop transfers in progress. The following procedure can be used by the
DCD to stop a transfer in progress:
The
Controller.
The following errors can occur:
1. Write a ‘1’ to the corresponding bit(s) in ENDPTFLUSH.
2. Wait until all bits in ENDPTFLUSH are ‘0’.
3. Read ENDPTSTAT to ensure that for all endpoints commanded to be flushed, that the
Overflow: Number of bytes received exceeded max. packet size or total buffer length.
This error will also set the Halt bit in the dQH, and if there are dTDs remaining in the
linked list for the endpoint, then those will not be executed.
ISO packet error: CRC Error on received ISO packet. Contents not guaranteed to be
correct.
ISO fulfillment error: Host failed to complete the number of packets defined in the dQH
mult field within the given (micro) frame. For scheduled data delivery the DCD may need
to readjust the data queue because a fulfillment error will cause Device Controller to
cease data transfers on the pipe for one (micro) frame. During the “dead” (micro) frame,
the Device Controller reports error on the pipe and primes for the following frame
Remark: Software note: This operation may take a large amount of time depending
on the USB bus activity. It is not desirable to have this wait loop within an interrupt
service routine.
corresponding bits are now ‘0’. If the corresponding bits are ‘1’ after step #2 has
finished, then the flush failed as described in the following:
In very rare cases, a packet is in progress to the particular endpoint when
commanded flush using ENDPTFLUSH. A safeguard is in place to refuse the flush to
ensure that the packet in progress completes successfully. The DCD may need to
repeatedly flush any endpoints that fail to flush by repeating steps 1-3 until each
endpoint is successfully flushed.
Table 354
354).
summarizes packet errors that are not automatically handled by the Device
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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