LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 442

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
21.6.2 USB Command register (USBCMD)
Table 364. HCCPARAMS register (HCCPARAMS - address 0x4000 7108) bit description
Table 365. DCIVERSION register (DCIVERSION - address 0x4000 7120) bit description
Table 366. DCCPARAMS (address 0x4000 7124)
The host/device controller executes the command indicated in this register.
Bit
0
1
2
7:4
15:8
31:9
Bit
15:0
31:16
Bit
4:0
6:5
7
8
31:9
Symbol
ADC
PFL
ASP
IST
Symbol
Symbol
DEN
-
DC
HC
-
EECP
-
DCIVERSION The device controller interface conforms to the
-
All information provided in this document is subject to legal disclaimers.
Description
Device Endpoint Number.
These bits are reserved and should be set to zero.
Device Capable.
Host Capable.
These bits are reserved and should be set to zero.
Description
64-bit Addressing Capability. If zero, no 64-bit
addressing capability is supported.
Programmable Frame List Flag. If set to one, then
the system software can specify and use a smaller
frame list and configure the host controller via the
USBCMD register Frame List Size field. The frame
list must always be aligned on a 4K-boundary. This
requirement ensures that the frame list is always
physically contiguous.
Asynchronous Schedule Park Capability. If this bit is
set to a one, then the host controller supports the
park feature for high-speed queue heads in the
Asynchronous Schedule.The feature can be
disabled or enabled and set to a specific level by
using the Asynchronous Schedule Park Mode
Enable and Asynchronous Schedule Park Mode
Count fields in the USBCMD register.
Isochronous Scheduling Threshold. This field
indicates, relative to the current position of the
executing host controller, where software can
reliably update the isochronous schedule.
EHCI Extended Capabilities Pointer. This optional
field indicates the existence of a capabilities list.
These bits are reserved and should be set to zero.
Rev. 00.13 — 20 July 2011
Description
two-byte BCD encoding of the interface version
number contained in this register.
These bits are reserved and should be set to
zero.
Chapter 21: LPC18xx USB1 Host/Device controller
Reset value Access
0x4
-
0x1
0x1
-
Reset value Access
0x1
-
-
Reset value Access
0
1
1
0
0
UM10430
© NXP B.V. 2011. All rights reserved.
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