LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 118

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 92.
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Symbol
CORE_RST
PERIPH_RST
MASTER_RST
-
WWDT_RST
CREG_RST
-
-
BUS_RST
SCU_RST
PINMUX_RST
-
-
M3_RST
-
-
LCD_RST
USB0_RST
USB1_RST
DMA_RST
SDIO_RST
EMC_RST
ETHERNET_RST
AES_RST
-
-
-
-
Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description
Description
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after three clock cycles.
Writing a one activates the reset. This bit is automatically cleared to 0
after three clock cycles.
Reserved
Writing a one to this bit has no effect.
Writing a one to this bit has no effect.
Reserved
Reserved
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle. Do not use during normal operation
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Reserved
Reserved
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Reserved
Reserved
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.
Reserved
Reserved
Reserved
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 11: LPC18xx Reset Generation Unit (RGU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
118 of 1164
Access
W
W
W
-
-
-
-
-
W
W
W
-
-
W
-
-
W
W
W
W
W
W
W
W
-
-
-
-