LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1163

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
42.4.6.4
42.4.6.4.1 PLL1 status register . . . . . . . . . . . . . . . . . . . 988
42.4.6.4.2 PLL1 control register . . . . . . . . . . . . . . . . . . 988
42.4.6.5
42.4.6.6
42.4.6.7
42.4.6.8
42.4.6.9
42.4.6.10 Output stage 3 to 19 control registers. . . . . . 993
42.4.6.11 Output stage 20 register . . . . . . . . . . . . . . . . 994
42.4.7
42.4.7.1
42.4.7.2
42.4.7.3
42.4.7.4
42.4.7.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
42.4.7.4.2 PLL0 description. . . . . . . . . . . . . . . . . . . . . . 997
42.4.7.4.3 Use of PLL0 operating modes . . . . . . . . . . . 998
42.4.7.4.4 Settings for USB0 . . . . . . . . . . . . . . . . . . . 1000
42.4.7.4.5 Usage notes . . . . . . . . . . . . . . . . . . . . . . . . 1000
42.4.7.5
42.4.7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
42.4.7.5.2 PLL1 description. . . . . . . . . . . . . . . . . . . . . 1001
42.4.8
42.4.8.1
42.4.8.2
42.5
42.5.1
42.5.2
42.5.3
42.5.4
42.5.5
42.5.5.1
42.5.5.2
42.5.5.3
42.5.5.4
42.6
42.6.1
42.7
42.7.1
42.7.2
42.7.3
42.7.3.1
42.7.3.2
42.7.3.3
42.7.3.4
<Document ID>
User manual
1015
LPC1850/30/20/10 Rev ‘-’ CCU . . . . . . . . . . 1004
LPC1850/30/20/10 Rev ‘-’ Pin configuration . . . .
LPC1850/30/20/10 Rev ‘-’ SCU . . . . . . . . . . 1039
PLL1 registers . . . . . . . . . . . . . . . . . . . . . . . 988
Integer divider register A . . . . . . . . . . . . . . . 989
Integer divider register B, C, D . . . . . . . . . . . 990
Integer divider register E . . . . . . . . . . . . . . . 991
Output stage 0 control register . . . . . . . . . . . 992
Output stage 1 control register . . . . . . . . . . . 992
Functional description. . . . . . . . . . . . . . . . . . 995
32 kHz oscillator . . . . . . . . . . . . . . . . . . . . . . 995
IRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 995
PLL0 (for USB0) . . . . . . . . . . . . . . . . . . . . . . 997
PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Pre-divider . . . . . . . . . . . . . . . . . . . . . . . . . .1002
Post-divider. . . . . . . . . . . . . . . . . . . . . . . . . .1002
Feedback divider . . . . . . . . . . . . . . . . . . . . .1002
Changing the divider values . . . . . . . . . . . . .1002
Integer mode . . . . . . . . . . . . . . . . . . . . . . . .1002
Non-integer mode . . . . . . . . . . . . . . . . . . . . .1003
Direct mode . . . . . . . . . . . . . . . . . . . . . . . . .1003
Power-down mode . . . . . . . . . . . . . . . . . . . .1003
Example CGU configurations . . . . . . . . . . . 1003
Programming the CGU for Deep-sleep and
Power-down modes . . . . . . . . . . . . . . . . . . 1003
Programming the CGU for using I2S at peripheral
clock rate of 30 MHz . . . . . . . . . . . . . . . . . . 1004
How to read this chapter. . . . . . . . . . . . . . . 1004
Basic configuration . . . . . . . . . . . . . . . . . . . 1005
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
General description . . . . . . . . . . . . . . . . . . 1005
Register description . . . . . . . . . . . . . . . . . . 1008
Power mode register . . . . . . . . . . . . . . . . . 1011
Base clock status register. . . . . . . . . . . . . . 1012
CCU1/2 branch clock configuration registers . . . .
1013
CCU1/2 branch clock status registers . . . . 1014
Pin description . . . . . . . . . . . . . . . . . . . . . . 1015
How to read this chapter. . . . . . . . . . . . . . . 1039
Basic configuration . . . . . . . . . . . . . . . . . . . 1039
General description . . . . . . . . . . . . . . . . . . 1040
Digital pin function . . . . . . . . . . . . . . . . . . . 1040
Digital pin mode . . . . . . . . . . . . . . . . . . . . . 1040
I
USB1 DP1/DM1 pins . . . . . . . . . . . . . . . . . 1040
2
C0-bus pins . . . . . . . . . . . . . . . . . . . . . . . 1040
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
42.7.3.5
42.7.4
42.7.4.1
42.7.4.2
42.7.4.3
42.7.4.4
42.7.4.5
42.7.4.6
42.7.4.7
42.7.4.8
42.7.4.9
42.7.4.10 EMC address delay register 1 . . . . . . . . . . 1052
42.7.4.11 EMC address delay register 2 . . . . . . . . . . 1052
42.7.4.12 EMC data in delay register . . . . . . . . . . . . 1053
42.8
42.8.1
42.8.2
42.8.3
42.8.4
42.8.4.1
42.8.4.2
42.8.4.3
42.8.4.4
42.8.4.5
42.9
42.9.1
42.9.2
42.9.3
42.9.4
42.9.5
42.9.6
42.9.6.1
42.9.6.2
42.9.6.3
42.9.6.4
42.9.6.5
42.9.6.6
42.9.6.7
42.9.6.8
42.9.6.9
42.9.6.9.1 Notes on fractional rate generators . . . . . . 1070
42.9.6.10 I2S Receive Clock Rate register . . . . . . . . 1071
42.9.6.11 I2S Transmit Clock Bit Rate register . . . . . 1071
42.9.6.12 I2S Receive Clock Bit Rate register . . . . . 1071
42.9.6.13 I2S Transmit Mode Control register . . . . . 1072
42.9.6.14 I2S Receive Mode Control register . . . . . . 1072
42.9.7
42.9.7.1
42.9.7.2
42.9.7.3
42.10
42.10.1
42.10.2
42.10.3
42.10.4
LPC1850/30/20/10 Rev ‘-’ GPIO . . . . . . . . . 1054
LPC1850/30/20/10 Rev ‘-’ I2S. . . . . . . . . . . 1061
LPC1850/30/20/10 Rev ‘-’ C_CAN . . . . . . . 1080
EMC signal delay control . . . . . . . . . . . . . . 1040
Register description . . . . . . . . . . . . . . . . . . 1041
Pin configuration registers for pins P0_n to PF_n
and CLK0 to CLK3 . . . . . . . . . . . . . . . . . . . 1047
Pin configuration register for USB1 pins DP1/DM1
1047
Pin configuration register for open-drain I
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
EMC clock delay register . . . . . . . . . . . . . . 1048
EMC control delay register. . . . . . . . . . . . . 1049
EMC chip select delay register . . . . . . . . . 1049
EMC data out delay register . . . . . . . . . . . 1050
EMC feedback clock delay register . . . . . . 1051
EMC address delay register 0 . . . . . . . . . . 1051
Basic configuration. . . . . . . . . . . . . . . . . . . 1054
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
Pin description . . . . . . . . . . . . . . . . . . . . . . 1054
Register description . . . . . . . . . . . . . . . . . . 1054
GPIO port direction register (DIR) . . . . . . . 1056
GPIO port mask register (MASK). . . . . . . . 1057
GPIO port pin value register (PIN) . . . . . . . 1058
GPIO port output set register (SET). . . . . . 1059
GPIO port output clear register (CLR) . . . . 1060
How to read this chapter . . . . . . . . . . . . . . 1061
Basic configuration. . . . . . . . . . . . . . . . . . . 1061
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
General description . . . . . . . . . . . . . . . . . . 1062
Pin description . . . . . . . . . . . . . . . . . . . . . . 1064
Register description . . . . . . . . . . . . . . . . . . 1066
I2S Digital Audio Output register . . . . . . . . 1066
I2S Digital Audio Input register . . . . . . . . . 1067
I2S Transmit FIFO register . . . . . . . . . . . . 1067
Receive FIFO register . . . . . . . . . . . . . . . . 1068
I2S Status Feedback register. . . . . . . . . . . 1068
I2S DMA Configuration Register 1 . . . . . . 1068
I2S DMA Configuration Register 2 . . . . . . 1069
I2S Interrupt Request Control register . . . . 1069
I2S Transmit Clock Rate register . . . . . . . 1070
Functional description . . . . . . . . . . . . . . . . 1073
I
I
FIFO controller . . . . . . . . . . . . . . . . . . . . . . 1078
How to read this chapter . . . . . . . . . . . . . . 1080
Basic configuration. . . . . . . . . . . . . . . . . . . 1080
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
General description . . . . . . . . . . . . . . . . . . 1081
2
2
S transmit and receive interfaces . . . . . . 1073
S operating modes . . . . . . . . . . . . . . . . . 1074
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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