LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 643

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 552. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description
<Document ID>
User manual
Bit
11
12
13
14
15
16
17
18
19
20
21
22
23
31:24 -
Symbol
CAP1MCI2_FE
CAP2MCI0_RE
CAP2MCI0_FE
CAP2MCI1_RE
CAP2MCI1_FE
CAP2MCI2_RE
CAP2MCI2_FE
RT0
RT1
RT2
HNFCAP0
HNFCAP1
HNFCAP2
26.7.2.2 MCPWM Capture Control set address
Writing ones to this write-only address sets the corresponding bits in CAPCON.
Table 553. MCPWM Capture Control set address (CAPCON_SET - 0x400A 0010) bit
Bit
0
1
2
3
4
5
6
7
8
9
Description
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.
A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.
A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.
A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.
A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.
A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.
A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.
If this bit is 1, TC0 is reset by a channel 0 capture event.
If this bit is 1, TC1 is reset by a channel 1 capture event.
If this bit is 1, TC2 is reset by a channel 2 capture event.
Hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in
Section
Hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in
Section
Hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in
Section
Reserved.
Symbol
CAP0MCI0_RE_SET
CAP0MCI0_FE_SET
CAP0MCI1_RE_SET
CAP0MCI1_FE_SET
CAP0MCI2_RE_SET
CAP0MCI2_FE_SET
CAP1MCI0_RE_SET
CAP1MCI0_FE_SET
CAP1MCI1_RE_SET
CAP1MCI1_FE_SET
26.8.4.
26.8.4.
26.8.4.
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Description
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
Writing a one sets the corresponding bits in the CAPCON
register.
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
-
-
-
-
-
-
-
-
-
-
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
-