LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 718

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the
IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the
type of interrupt and handling as described in
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART Rx error
condition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared upon
a LSR read.
The UART RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the
trigger level defined in FCR7:6 and is reset when the UART Rx FIFO depth falls below the
trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the UART Rx
FIFO contains at least one character and no UART Rx FIFO activity has occurred in 3.5 to
4.5 character times. Any UART Rx FIFO activity (read or write of UART RSR) will clear the
interrupt. This interrupt is intended to flush the UART RBR after a message has been
received that is not a multiple of the trigger level size. For example, if a peripheral wished
to send a 105 character message and the trigger level was 10 characters, the CPU would
receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI
interrupts (depending on the service routine) resulting in the transfer of the remaining 5
characters.
Table 670. UART Interrupt Handling
IIR[3:0]
value
0001
0110
0100
1100
0010
[1]
Priority Interrupt
-
Highest RX Line
Second RX Data
Second Character
Third
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type
None
Status /
Error
Available
Time-out
indication
THRE
Rev. 00.13 — 20 July 2011
Interrupt source
None
OE
Rx data available or trigger level reached in
FIFO (FCR0=1)
Minimum of one character in the RX FIFO and
no character input or removed during a time
period depending on how many characters are
in FIFO and what the trigger level is set at (3.5 to
4.5 character times).
The exact time will be:
[(word length)  7 - 2]  8 + [(trigger level -
number of characters)  8 + 1] RCLKs
THRE
[2]
or PE
[2]
[2]
or FE
Table
[2]
670. Given the status of IIR[3:0], an
Chapter 32: LPC18xx USART0_2_3
or BI
[2]
UM10430
© NXP B.V. 2011. All rights reserved.
Interrupt
reset
-
LSR Read
RBR
Read
UART FIFO
drops below
trigger level
RBR
Read
IIR Read
(if source of
interrupt) or
THR write
718 of 1164
[3]
[3]
or
[4]
[2]