LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 956

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.1.8.13 Interrupt Priority Register 7
42.1.8.14 Software Trigger Interrupt Register (STIR - 0xE000 EF00)
Table 898. Interrupt Priority Register 6 (IPR6 - address 0xE000 E418) bit description
The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 899. Interrupt Priority Register 7 (IPR7 - address 0xE000 E41C) bit description
The STIR register provides an alternate way for software to generate an interrupt, in
addition to using the ISPR registers. This mechanism can only be used to generate
peripheral interrupts, not system exceptions.
By default, only privileged software can write to the STIR register. Unprivileged software
can be given this ability if privileged software sets the USERSETMPEND bit in the CCR
register.
Table 900. Software Trigger Interrupt Register (STIR - address 0xE000 EF00) bit description
Bit
15:11 IP_UART1
18:16 -
23:19 IP_USART2 USART2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
26:24 -
31:27 IP_USART3 USART3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
Bit
2:0
7:3
10:8
15:11 IP_AES
18:16 -
23:19 IP_SPIFI SPIFI interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
31:24 -
Bit
8:0
31:9
Symbol
Symbol
-
IP_I2S
-
Symbol
INTID
-
All information provided in this document is subject to legal disclaimers.
Description
Reserved.These bits ignore writes, and read as 0.
I2S interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Reserved.These bits ignore writes, and read as 0.
AES interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Reserved.These bits ignore writes, and read as 0.
Reserved.These bits ignore writes, and read as 0.
Description
Writing a value to this field generates an interrupt for the specified
Interrupt ID (see
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
UART1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Reserved.These bits ignore writes, and read as 0.
priority.
Reserved.These bits ignore writes, and read as 0.
priority.
Rev. 00.13 — 20 July 2011
Table
885).
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
956 of 1164
Reset
value
0
0
0
0
0
Reset
value
0
0
0
0
0
0
0
Reset
value
-