LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 662

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.8.2 Shadow registers and simultaneous updates
26.8.3 Fast Abort (ABORT)
26.8.4 Capture events
The Limit, Match, and Communication Pattern registers (LIM, MAT, and CP) are
implemented as register pairs, each consisting of a write register and an operational
register. Software writes into the write registers. The operational registers control the
actual operation of each channel and are loaded with the current value in the write
registers when the TC starts counting up from 0.
Updating of the functional registers can be disabled by setting a channel’s DISUP bit in
the CON register. If the DISUP bits are set, the functional registers are not updated until
software stops the channel.
If a channel is not running when software writes to its LIM or MAT register, the functional
register is updated immediately.
Software can write to a TC register only when its channel is stopped.
The MCPWM has an external input MCABORT. When this input goes low, all six MCO
outputs assume their “A passive” states, and the Abort interrupt is generated if enabled.
The outputs remain locked in “A passive” state until the ABORT interrupt flag is cleared or
the Abort interrupt is disabled. The ABORT flag may not be cleared before the MCABORT
input goes high.
In order to clear an ABORT flag, a 1 must be written to bit 15 of the INTF_CLR register.
This will remove the interrupt request. The interrupt can also be disabled by writing a 1 to
bit 15 of the INTEN_CLR register.
Each PWM channel can take a snapshot of its TC when an input signal transitions. Any
channel may use any combination of rising and/or falling edges on any or all of the MCI0-2
inputs as a capture event, under control of the CAPCON register. Rising or falling edges
on the inputs are detected synchronously with respect to PCLK.
Fig 77. Center-aligned waveform with dead time, POLA = 0
MCOB
MCOA
All information provided in this document is subject to legal disclaimers.
0
active
passive
Rev. 00.13 — 20 July 2011
MAT
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
DT
active
passive
LIM
MAT
DT
passive
active
0
LIM
passive
UM10430
DT
active
© NXP B.V. 2011. All rights reserved.
POLA = 0
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