LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 616

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.7.10.1.3 Configure events and event responses
1. Define when each event can occur in the following way in the EVCTRL registers (up
2. Define what the effect of each event is on the SCT’s outputs in the OUTPUTSET or
3. Define how each event affects the counter:
4. Define which events contribute to the SCT interrupt:
5. Define whether an event triggers a DMA request.
– Each match reload register MATCHRELOAD allows to set a reload value that is
to 16, one register per event):
– Select whether the event occurs on an input or output changing, on an input or
– For a match condition:
– For an SCT input or output level or transition:
OUTPUTCLR registers (up to 16 outputs, one register per output):
– For each SCT output, select which events set or clear this output. An output can be
– Set the corresponding event bit in the LIMIT register for the event to set an upper
– Set the corresponding event bit in the HALT register for the event to halt the
– Set the corresponding event bit in the STOP register for the event to stop the
– Set the corresponding event bit in the START register for the event to restart the
– Set the corresponding event bit in the EVEN and the EVFLAG registers to enable
loaded into the match register when the counter reaches a limit condition or the
value 0.
output level, a match condition of the counter, or a combination of match and
input/output conditions in field COMBMODE.
Select the match register that contains the match condition for the event to occur.
Enter the number of the selected match register in field MATCHSEL.
If using L and H counters, define whether the event occurs on matching the L or
the H counter in field HEVENT.
Select the input number or the output number that is associated with this event in
fields IOSEL and OUTSEL.
Define how the selected input or output triggers the event (edge or level sensitive)
in field IOCOND.
changed by more than one event, and each event can change multiple outputs.
limit for the counter.
When a limit event occurs in unidirectional mode, the counter is cleared to zero
and begins counting up on the next clock edge.
When a limit event occurs in bidirectional mode, the counter begins to count down
from the current value on the next clock edge.
counter. If the counter is halted, it stops counting and no new events can occur.
The counter operation can only be restored by clearing the HALT_L and/or the
HALT_H bits in the CTRL register.
counter. If the counter is stopped, it stops counting but can be restarted by an
event that is configured as an transition on an input/output.
counting. Only events that are defined by an input changing can be used to restart
the counter.
the event to contribute to the SCT interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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