LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 802

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 745. I2S receive modes
<Document ID>
User manual
DAI bit 5
0
0
0
0
1
1
1
RXMODE bit
[3:0]
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
0 0 0 0
0 0 1 0
0 1 0 0
Description
Typical receiver master mode. See
The I2S receive function operates as a master.
The receive clock source is the fractional rate divider.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is not enabled for output.
Receiver master mode sharing the transmitter reference clock. See
The I2S receive function operates as a master.
The receive clock source is TX_REF.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is not enabled for output.
4-wire receiver master mode sharing the transmitter bit clock and WS. See
The I2S receive function operates as a master.
The receive clock source is the TX bit clock.
The WS used is the internally generated TX_WS.
The RX_MCLK pin is not enabled for output.
Receiver master mode with RX_MCLK output. See
The I2S receive function operates as a master.
The receive clock source is the fractional rate divider.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is enabled for output.
Typical receiver slave mode. See
The I2S receive function operates as a slave.
The receive clock source is the RX_SCK pin.
The WS used is the RX_WS pin.
Receiver slave mode sharing the transmitter reference clock. See
The I2S receive function operates as a slave.
The receive clock source is TX_REF.
The WS used is the RX_WS pin.
This is a 4-wire receiver slave mode sharing the transmitter bit clock and WS. See
Figure
The I2S receive function operates as a slave.
The receive clock source is the TX bit clock.
The WS used is TX_WS ref.
121.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Figure
Figure
119.
116.
Figure
Chapter 35: LPC18xx I2S interface
116.
Figure
Figure
UM10430
© NXP B.V. 2011. All rights reserved.
120.
117.
Figure
118.
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