LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 320

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
18.6.35 Internal DMAC Interrupt Enable Register (IDINTEN)
18.6.36 Current Host Descriptor Address Register (DSCADDR)
Table 259. Internal DMAC Interrupt Enable Register (IDINTEN, address 0x4000 4090) bit
Table 260. Current Host Descriptor Address Register (DSCADDR, address 0x4000 4094) bit
Bit
0
1
2
3
4
5
7:6
8
9
31:10
Bit
31:0
Symbol
TI
RI
FBE
-
DU
CES
-
NIS
AIS
-
Symbol
HDA
description
description
All information provided in this document is subject to legal disclaimers.
Description
Host Descriptor Address Pointer. Cleared on reset. Pointer
updated by IDMAC during operation. This register points to
the start address of the current descriptor read by the IDMAC.
Rev. 00.13 — 20 July 2011
Description
Transmit Interrupt Enable. When set with Normal Interrupt
Summary Enable, Transmit Interrupt is enabled. When
reset, Transmit Interrupt is disabled.
Receive Interrupt Enable. When set with Normal Interrupt
Summary Enable, Receive Interrupt is enabled. When
reset, Receive Interrupt is disabled.
Fatal Bus Error Enable. When set with Abnormal Interrupt
Summary Enable, the Fatal Bus Error Interrupt is enabled.
When reset, Fatal Bus Error Enable Interrupt is disabled.
Reserved
Descriptor Unavailable Interrupt. When set along with
Abnormal Interrupt Summary Enable, the DU interrupt is
enabled.
Card Error summary Interrupt Enable. When set, it enables
the Card Interrupt summary.
Reserved
Normal Interrupt Summary Enable. When set, a normal
interrupt is enabled. When reset, a normal interrupt is
disabled. This bit enables the following bits: IDINTEN[0] -
Transmit Interrupt IDINTEN[1] - Receive Interrupt
Abnormal Interrupt Summary Enable. When set, an
abnormal interrupt is enabled. This bit enables the
following bits: IDINTEN[2] - Fatal Bus Error Interrupt
IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error
Summary Interrupt
Reserved
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
320 of 1164
Reset
value
0
0
0
0
0
0
0