LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 733

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.16 UART RS485 Address Match register
Table 682. UART RS485 Control register (RS485CTRL - addresses 0x4008 104C (UART0),
After reset RS485 mode will be disabled. The RS485 feature allows the USART to be
configured as one of multiple addressable slave receivers controlled by a single USART.
In RS485 mode the USART differentiates between an address character and a data
character by means of a ninth bit. The parity bit is used to implement this bit, and when set
to ‘1’ indicates an address and when set to ‘0’ indicates data. RS485 mode is enabled by
setting the NMMEN bit. The USART slave receiver can be assigned a unique address
and, manually or automatically, reject or accept data based on a received address. See
section
The RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
Table 683. UART RS485 Address Match register (RS485ADRMATCH - addresses 0x4008 1050
Bit
1
2
3
4
5
31:6 -
Bit
7:0
31:8
Symbol
RXDIS
AADEN
-
DCTRL
OINV
Section 32.6.3
Symbol
ADRMATCH
-
0x400C 104C (UART2), 0x400C 204C (UART3)) bit description
(UART0), 0x400C 1050 (UART2), 0x400C 2050 (UART3)) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
-
0
1
0
1
-
Rev. 00.13 — 20 July 2011
for details.
Description
Contains the address match value.
Reserved
Description
Receiver enable.
The receiver is enabled.
The receiver is disabled.
AAD enable
Auto Address Detect (AAD) is disabled.
Auto Address Detect (AAD) is enabled.
Reserved.
Direction control for DIR pin.
Disable Auto Direction Control.
Enable Auto Direction Control.
Direction control pin polarity.
This bit reverses the polarity of the direction
control signal on the DIR pin.
The direction control pin will be driven to logic ‘0’
when the transmitter has data to be sent. It will be
driven to logic ‘1’ after the last bit of data has been
transmitted.
The direction control pin will be driven to logic ‘1’
when the transmitter has data to be sent. It will be
driven to logic ‘0’ after the last bit of data has been
transmitted.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Chapter 32: LPC18xx USART0_2_3
UM10430
…continued
© NXP B.V. 2011. All rights reserved.
Reset value
0x00
-
Reset
value
0
0
-
0
0
NA
733 of 1164