LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 485

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 404. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description
<Document ID>
User manual
Bit
7:6
8
9
30:10
31
Symbol
PCF
SAIF
SAF
-
RA
22.6.3 MAC Hash table high register
Description
Pass Control Frames
These bits control the forwarding of all control frames (including unicast and multicast
PAUSE frames). Note that the processing of PAUSE control frames depends only on
RFE of Flow Control Register[2].
00 = MAC filters all control frames from reaching the application.
01 = MAC forwards all control frames except PAUSE control frames to application
even if they fail the Address filter.
10 = MAC forwards all control frames to application even if they fail the Address Filter.
11 = MAC forwards control frames that pass the Address Filter.
SA Inverse Filtering
When this bit is set, the Address Check block operates in inverse filtering mode for
the SA address comparison. The frames whose SA matches the SA registers will be
marked as failing the SA Address filter.
When this bit is reset, frames whose SA does not match the SA registers will be
marked as failing the SA Address filter.
Source Address Filter Enable
The MAC core compares the SA field of the received frames with the values
programmed in the enabled SA registers. If the comparison matches, then the
SAMatch bit of RxStatus Word is set high. When this bit is set high and the SA filter
fails, the MAC drops the frame.
When this bit is reset, then the MAC Core forwards the received frame to the
application and with the updated SA Match bit of the RxStatus depending on the SA
address comparison.
Reserved
Receive all
When this bit is set, the MAC Receiver module passes to the Application all frames
received irrespective of whether they pass the address filter. The result of the SA/DA
filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word.
When this bit is reset, the Receiver module passes to the Application only those
frames that pass the SA/DA address filter.
The 64-bit Hash table is used for group address filtering. For hash filtering, the contents of
the destination address in the incoming frame is passed through the CRC logic, and the
upper 6 bits of the CRC register are used to index the contents of the Hash table. The
most significant bit determines the register to be used (Hash Table High/Hash Table Low),
and the other 5 bits determine which bit within the register. A hash value of 00000 selects
Bit 0 of the selected register, and a value of 11111 selects Bit 31 of the selected register.
the first byte received on MII interface), then the internally calculated 6-bit Hash value is
0x2C and the HTH register bit[12] is checked for filtering. If the DA of the incoming frame
is received as 0xA00A98000045, then the calculated 6- bit Hash value is 0x07 and the
HTL register bit[7] is checked for filtering.
rejected. If the PM (Pass All Multicast) bit is set in the MAC_CONFIG register, then all
multicast frames are accepted regardless of the multicast hash values.
For example, if the DA of the incoming frame is received as 0x1F52419CB6AF (0x1F is
If the corresponding bit value of the register is 1, the frame is accepted. Otherwise, it is
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
…continued
Reset
value
00
0
0
0
0
485 of 1164
Access
R/W
R/W
R/W
RO
R/W