LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 323

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
19.4 General description
<Document ID>
User manual
Remark: Synchronous static memory devices (synchronous burst mode) are not
supported.
The LPC18xx External Memory Controller (EMC) is an ARM PrimeCell MultiPort Memory
Controller peripheral offering support for asynchronous static memory devices such as
RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM.
The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral.
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Read and write buffers to reduce latency and to improve performance.
8-bit, 16-bit, and 32-bit wide static memory support.
16-bit and 32-bit wide chip select SDRAM memory support.
Static memory features include:
– Asynchronous page mode read
– Programmable wait states
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
Four chip selects for synchronous memory and four chip selects for static memory
devices.
Power-saving modes dynamically control EMC_CKE and EMC_CLK to SDRAMs.
Dynamic memory self-refresh mode controlled by software.
Controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts.
That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per
device.
Separate reset domains allow the for auto-refresh through a chip reset if desired.
Programmable delay elements allow fine-tuning EMC timing.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
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