LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 388

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 329. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description
<Document ID>
User manual
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol Value
IDIS
AVVIS
ASVIS
BSVIS
BSEIS
ms1S
DPIS
-
IDIE
AVVIE
ASVIE
BSVIE
BSEIE
-
Description
USB ID interrupt status
This bit is set when a change on the ID input has been detected.
Software must write a 1 to this bit to clear it.
A-VBUS valid interrupt status
This bit is set then VBUS has either risen above or fallen below the
A-VBUS valid threshold (4.4 V on an A-device).
Software must write a 1 to this bit to clear it.
A-Session valid interrupt status
This bit is set then VBUS has either risen above or fallen below the
A-session valid threshold (0.8 V).
Software must write a 1 to this bit to clear it.
B-Session valid interrupt status
This bit is set then VBUS has either risen above or fallen below the
B-session valid threshold (0.8 V).
Software must write a 1 to this bit to clear it.
B-Session end interrupt status
This bit is set then VBUS has fallen below the B-session end threshold.
Software must write a 1 to this bit to clear it.
1 millisecond timer interrupt status
This bit is set once every millisecond.
Software must write a 1 to this bit to clear it.
Data pulse interrupt status
This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing
is only detected when the CM bit in USBMODE = Host (11) and the
PortPower bit in PORTSC = Off (0).
Software must write a 1 to this bit to clear it.
reserved
USB ID interrupt enable
Setting this bit enables the interrupt. Writing a 0 disables the interrupt.
A-VBUS valid interrupt enable
Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the
interrupt.
A-session valid interrupt enable
Setting this bit enables the A-session valid interrupt. Writing a 0 disables
the interrupt
B-session valid interrupt enable
Setting this bit enables the B-session valid interrupt. Writing a 0 disables
the interrupt.
B-session end interrupt enable
Setting this bit enables the B-session end interrupt. Writing a 0 disables the
interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
…continued
UM10430
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
© NXP B.V. 2011. All rights reserved.
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