LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 861

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.7.6 I
The values for SCLL and SCLH must ensure that the data rate is in the appropriate I
data rate range. Each register value must be greater than or equal to 4.
some examples of I
values.
Table 808. SCLL + SCLH values for selected I
SCLL and SCLH values should not necessarily be the same. Software can set different
duty cycles on SCL by setting these two registers. For example, the I
defines the SCL low time and high time at different values for a Fast-mode and Fast-mode
Plus I
The CONCLR registers control clearing of bits in the CON register that controls operation
of the I
the I
Table 809. I
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
CONSET register. Writing 0 has no effect.
I
Standard mode
Fast-mode
Fast-mode Plus
Bit
1:0
2
3
4
5
6
7
31:8 -
2
2
C mode
C Control Clear register
2
C control register to be cleared. Writing a zero has no effect.
2
Symbol
-
AAC
SIC
-
STAC
I2ENC
-
C.
2
C interface. Writing a one to a bit of this register causes the corresponding bit in
(I2C1)) bit description
2
C Control Clear register (CONCLR - address 0x400A 1018 and 0x400E 0018
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
START flag Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Reserved. The value read from a reserved bit is not defined.
2
2
1 MHz
C interrupt Clear bit.
C interface Disable bit.
I
frequency
100 kHz
400 kHz
2
C bit
2
C-bus rates based on I2C_PCLK frequency and SCLL and SCLH
Rev. 00.13 — 20 July 2011
I 2 C
bitfrequency
6
60
15
-
8
80
20
8
=
-------------------------------------------------------- -
I2CSCLH
100
25
10
10
2
C clock values
Chapter 37: LPC18xx I2C-bus interface
I2CPCLK
120
30
12
12
I2C_PCLK (MHz)
SCLH + SCLL
+
I2CSCLL
16
160
40
16
20
200
50
20
2
30
300
75
30
C-bus specification
UM10430
© NXP B.V. 2011. All rights reserved.
Table 808
40
400
100
40
861 of 1164
Reset
value
-
0
-
0
0
-
-
gives
50
500
125
50
2
C
(10)