LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1004

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
42.5 LPC1850/30/20/10 Rev ‘-’ CCU
<Document ID>
User manual
42.4.8.2 Programming the CGU for using I2S at peripheral clock rate of 30 MHz
42.5.1 How to read this chapter
When the LPC18xx wakes up from Deep-sleep or Power-down mode, the IRC is used as
the clock soures for all output stages. Also see
In this example the peripheral clock of the I2S interface is set to 30 MHz. The peripheral
I2S clock is a branch of the BASE_APB1_CLK. Using a crystal of 12 MHz as clock source,
a PLL1 multiplier of 10, and an integer divider of 4 provide the desired clock rate.
For this example, program the CGU as follows:
Remark: This chapter applies to parts LPC1850_30_20_10 Rev ‘-’.
Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. The
SDIO interface is not available. See <tbd>. The corresponding clock control registers and
register bits are reserved.
1. Enable the crystal oscillator in the XTAL_OSC_CTRL register
2. Wait for the crystal to stabilize.
3. Select the crystal oscillator as input to the PLL1 and set up the divider in the
4. Wait for the PLL1 to lock.
5. Select the PLL1 as clock source of the integer divider A (IDIVA) in the IDIVA register
6. Select IDIVA as clock source of the base clock BASE_APB1_CLK and set
7. Ensure that the I2S branch clock CLK_APB1_I2S is enabled in the CCU (see
XTAL_OSC
PLL1_CTRL register (see
– Set bits CLK_SEL in the PLL1_CTRL register to 0x6.
– Set MSEL = 9.
– Set NSEL = 0.
– Set PSEL = 1.
– Set FBSEL = 1.
– Set BYPASS = 0, DIRECT = 0.
and set AUTOBLOCK = 1 (see
AUTOBLOCK = 1 (see
Table
152).
12MHz
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
PLL1 x 10
Table
Table
943).
Table
938):
120MHz
939).
Section 8.2.3
DIVA / 4
30MHz
and
Section
Chapter 42: Appendix
(Table
UM10430
BASE_APB1_CLK
© NXP B.V. 2011. All rights reserved.
932).
8.2.4.
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