LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 65

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
8.4 Functional description
<Document ID>
User manual
8.4.1 Run-time programming
8.4.2 Power API
The PD0_SLEEP0_MODE register can be programmed at run-time to change the default
power state of the LPC18xx after the next transition to a reduced-power state. The default
state is Deep power-down corresponding to a reset value of the PD0_SLEEP0_MODE
register of 0x003F FF7F.
Table 42.
[1]
<tbd>
Power mode
Deep-sleep
Power-down
Deep power-down
When the IO pads are off, the external IO supply should be removed. Pin RTC_ALARM can be used to
indicate when the event router and the core become active and when the IO should be powered on.
Typical settings for PMC power modes
All information provided in this document is subject to legal disclaimers.
PD0_SLEEP0_MODE
register bit settings
0x0030 00AA
0x0030 FC3A
0x0030 FF7F
Rev. 00.13 — 20 July 2011
Chapter 8: LPC18xx Power Management Controller (PMC)
Description
CPU, peripherals, analog, USB PHY, and retention
supplies in retention mode; all SRAM supplies in
active mode; IO pads powered
power-down mode.
CPU, peripherals, analog supplies in retention
mode; USB PHY in power-down mode; retention in
retention mode; SRAM1 in active mode; all other
SRAMs in power-down mode; IO pads powered
BOD in power-down mode.
CPU, peripherals, analog, USB PHY in power-down
mode; all SRAMs, IO pads powered
power-down mode.
[1]
UM10430
© NXP B.V. 2011. All rights reserved.
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[1]
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[1]
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