LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 424

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.9 Isochronous endpoint operational model
Table 352. Control endpoint bus response matrix
[1]
[2]
[3]
Isochronous endpoints are used for real-time scheduled delivery of data, and their
operational model is significantly different than the host throttled Bulk, Interrupt, and
Control data pipes. Real time delivery by the device controller is accomplished by the
following:
exchanges to Isochronous endpoints. The operational model for device mode does not
use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt
endpoints is also used for isochronous endpoints. The difference is in the handling of the
dTD.
The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a
delayed operation such that an endpoint will become primed only after a SOF is received.
After the DCD writes the prime bit, the prime bit will be cleared as usual to indicate to
software that the device controller completed a priming the dTD for transfer. Internal to the
design, the device controller hardware masks that prime start until the next frame
boundary. This behavior is hidden from the DCD but occurs so that the device controller
can match the dTD to a specific (micro) frame.
Another difference with isochronous endpoints is that the transaction must wholly
complete in a (micro) frame. Once an ISO transaction is started in a (micro) frame it will
retire the corresponding dTD when MULT transactions occur or the device controller finds
Token
type
Setup
In
Out
Ping
Invalid
An EHCI compatible host controller uses the periodic frame list to schedule data
•
•
•
BS error = Force Bit Stuff Error
NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable
length protocol then ACK.
SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is
responsive.
Exactly MULT Packets per (micro) Frame are transmitted/received. Note: MULT is a
two-bit field in the device Queue Head. The variable length packet protocol is not
used on isochronous endpoints.
NAK responses are not used. Instead, zero length packets are sent in response to an
IN request to an unprimed endpoints. For unprimed RX endpoints, the response to an
OUT transaction is to ignore the packet within the device controller.
Prime requests always schedule the transfer described in the dTD for the next (micro)
frame. If the ISO-dTD is still active after that frame, then the ISO-dTD will be held
ready until executed or canceled by the DCD.
Endpoint sate
STALL Not primed Primed
ACK
STALL NAK
STALL NAK
STALL NAK
Ignore Ignore
All information provided in this document is subject to legal disclaimers.
ACK
Rev. 00.13 — 20 July 2011
ACK
Transmit
Receive and
NYET/ACK
ACK
Ignore
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Underflow
n/a
BS error
n/a
n/a
Ignore
Overflow
SYSERR
n/a
NAK
n/a
Ignore
UM10430
© NXP B.V. 2011. All rights reserved.
Setup lockout
-
n/a
n/a
n/a
ignore
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