LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 748

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 692: UART1 Divisor Latch LSB Register when DLAB = 1 (DLL - address 0x4008 2000 ) bit description
Table 693: UART1 Divisor Latch MSB Register when DLAB = 1 (DLM - address 0x4008 2004 ) bit description
Table 694: UART1 Interrupt Enable Register when DLAB = 0 (IER - address 0x4008 2004 ) bit description
<Document ID>
User manual
Bit
7:0
31:8
Bit
7:0
31:8
Bit
0
1
2
3
6:4
Symbol
RBRIE
THREIE
RXIE
MSIE
-
Symbol Description
DLLSB
-
Symbol Description
DLMSB
-
33.5.4 UART1 Interrupt Enable Register (when DLAB = 0)
Divisor Latch LSB.
The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the
baud rate of the UART1.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Divisor Latch MSB.
The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the
baud rate of the UART1.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Value Description
0
1
0
1
0
1
0
1
The U1IER is used to enable the four UART1 interrupt sources.
RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also
controls the Character Receive Time-out interrupt.
Disable the RDA interrupts.
Enable the RDA interrupts.
THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this
interrupt can be read from U1LSR[5].
Disable the THRE interrupts.
Enable the THRE interrupts.
RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of
this interrupt can be read from U1LSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Modem Status Interrupt Enable. Enables the modem interrupt. The status of this
interrupt can be read from U1MSR[3:0].
Disable the modem interrupt.
Enable the modem interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x01
NA
Reset value
0x00
NA
748 of 1164
Reset
value
0
0
0
0
NA