LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 859

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.7.2 I
37.7.3 I
SI is the I
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is
0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
Each I
Status register is Read-Only.
Table 803. I
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in DAT remains stable as long as the SI bit is set. Data in DAT is always
shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a byte
has been received, the first bit of received data is located at the MSB of DAT.
Bit
2:0
7:3
31:8
2
2
1. The address in the Slave Address Register has been received.
2. The General Call address has been received while the General Call bit (GC) in ADR is
3. A data byte has been received while the I
4. A data byte has been received while the I
1. A data byte has been received while the I
2. A data byte has been received while the I
C Status register
C Data register
set.
2
Symbol
-
Status
-
C Status register reflects the condition of the corresponding I
2
C Interrupt Flag. This bit is set when the I
bit description
2
C Status register (STAT - address 0x400A 1004 (I2C0) and 0x400E 0004 (I2C1))
All information provided in this document is subject to legal disclaimers.
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
interface.
Reserved. The value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
2
C states. When any of these states entered, the SI bit will
2
2
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode
C is in the master receiver mode.
C is in the addressed slave receiver mode.
Chapter 37: LPC18xx I2C-bus interface
2
C state changes. However, entering
Table 818
2
C
2
C interface. The I
UM10430
© NXP B.V. 2011. All rights reserved.
to
Table
Reset value
0
0x1F
-
859 of 1164
823.
2
C