LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 487

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 407. MAC MII Address register (MAC_MII_ADDR, address 0x4001 0010) bit description
<Document ID>
User manual
Bit
0
1
5:2
10:6
15:11
31:16
Symbol
GB
W
CR
GR
PA
-
Description
MII busy
This bit should read a logic 0 before writing to this register and the MAC_MII_DATA
register. This bit must also be set to 0 during a Write to this register. During a PHY
register access, this bit will be set to 1 by the Application to indicate that a Read or
Write access is in progress. The MAC_MII_DATA register should be kept valid until
this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA
register is invalid until this bit is cleared by the MAC during a PHY Read operation.
This register should not be written to until this bit is cleared.
MII write
When set, this bit tells the PHY that this will be a Write operation using the MII Data
register. If this bit is not set, this will be a Read operation, placing the data in the MII
Data register.
CSR clock range
The CSR Clock Range selection determines the frequency of the MDC clock . The
suggested range of clk_csr_i frequency applicable for each value below (when Bit[5]
= 0) ensures that the MDC clock is approximately between the frequency range 1.0
MHz - 2.5 MHz.
When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE
802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value.
For example, when clk_csr_i is of frequency 100 Mhz and you program these bits as
1010, then the resultant MDC clock will be of 12.5 Mhz which is outside the limit of
IEEE 802.3 specified range. Please program the values given below only if the
interfacing chips supports faster MDC clocks.
See
MII register
These bits select the desired MII register in the selected PHY device.
Physical layer address
This field tells which of the 32 possible PHY devices are being accessed.
Reserved
Table 408
Table 408. CSR clock range values
Bits 5:2
0000
0001
0010
0011
0100
0101
0110, 0111
1000
1001
1010
1011
1100
for bit values.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
clk_csr_i
60 - 100 MHz
100 - 150 MHz
20 - 35 MHz
35 - 60 MHz
150 - 250 MHz
250 - 300 MHz
Reserved
-
-
-
-
-
Chapter 22: LPC18xx Ethernet
MDC clock
clk_csr_i/42
clk_csr_i/62
clk_csr_i/16
clk_csr_i/26
clk_csr_i/102
clk_csr_i/124
-
clk_csr_i/42
clk_csr_i/62
clk_csr_i/16
clk_csr_i/26
clk_csr_i/102
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
487 of 1164
Access
R_WS_
SC
R/W
R/W
R/W
R/W
RO