LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 977

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
42.4 LPC1850/30/20/10 Rev ‘-’ CGU
<Document ID>
User manual
42.3.4.9 Part ID register
42.4.1 How to read this chapter
Table 923. CREG6 control register (CREG6, address 0x4004 312C) bit description
Table 924. Part ID register (CHIPID, address 0x4004 3200) bit description
Remark: This chapter refers to the LPC1850/30/20/10 Rev ‘-’ parts only. See
for a description of the CGU for Parts LPC1850/30/20/10 Rev ‘A’ and all LPC18xx parts
with on-chip flash.
Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. The
SDIO interface is not available. The corresponding clock control registers are reserved.
Bit
5:4
6
7
8
31:
9
Bit
31:0
Symbol
TIMIN7CTRL
TIM1INCTRL
TIM2INCTRL
TIM3INCTRL
-
Symbol
ID
All information provided in this document is subject to legal disclaimers.
Description
<tbd>
Value Description
0x0
0x1
0x2
0x3
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Controls the input to timer 3 (CAP2) and the SCT
(input 7):
I2S0 receive mws signal
I2S0 transmit mws signal
USB0 SOF signal
USB1 SOF signal
Controls the muxing of the timer1 CAP inputs
CAP1 and CAP2.
Timer1 CAP1 connected to pin CTIN_3; timer 1
CAP2 connected to CTIN_4.
Timer1 CAP1 connected to USART0 transmit wait;
timer 1 CAP2 connected to USART0 receive wait.
Controls the muxing of the timer 2 CAP inputs
CAP1 and CAP2.
Timer2 CAP1 connected to pin CTIN_1; timer 2
CAP2 connected to CTIN_4.
Timer2 CAP1 connected to USART2 transmit wait;
timer 2 CAP2 connected to USART2 receive wait.
Controls the muxing of the timer 3 CAP inputs
CAP1 and CAP2.
Timer3 CAP1 connected to pin CTIN_6; timer 3
CAP2 connected to combined timer input 7 (see
bits 5:4).
Timer2 CAP1 connected to USART3 transmit wait;
timer 2 CAP2 connected to USART3 receive wait.
Reserved.
Chapter 42: Appendix
UM10430
Reset
value
© NXP B.V. 2011. All rights reserved.
Reset
value
-
Chapter 9
Access
…continued
977 of 1164
-
Access
R/W
R/W
R/W
R/W