LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1051

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.7.4.8 EMC feedback clock delay register
42.7.4.9 EMC address delay register 0
Table 972. EMC data out delay register (EMCDOUTDELAY, address 0x4008 6D0C) bit
This register provides a programmable delay for the EMC feedback clocks (8 data lanes
per feedback clock). The delay for each control output is approximately 0.5 ns 
XXX_DELAY. (XXX_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay 
3.5 ns.)
Table 973. EMC DQM delay register (EMCFBCLKDELAY, address 0x4008 6D10) bit
This register provides a programmable delay for the EMC address outputs. The delay for
each control output is approximately 0.5 ns  ADDRn_DELAY. (ADDRn_DELAY = 0x0:
delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.)
Table 974. EMC address delay register 0 (EMCADDRDELAY0, address 0x4008 6D14) bit
Bit
27
30:28
31
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
31: 19 -
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
Symbol
-
D3_DELAY
-
Symbol
FBCLK0_DELAY Delay of the EMC feedback clock 0 (for byte lane 0). 0
-
FBCLK1_DELAY Delay of the EMC feedback clock 1 (for byte lane 1). 0
-
FBCLK2_DELAY Delay of the EMC feedback clock 2 (for byte lane 2). 0
-
FBCLK3_DELAY Delay of the EMC feedback clock 3 (for byte lane 3). 0
-
CCLK_DELAY
Symbol
ADDR0_DELAY
-
ADDR1_DELAY
-
ADDR2_DELAY
-
ADDR3_DELAY
-
ADDR4_DELAY
description
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
…continued
Description
Reserved.
Delay of the EXTBUS_D24 to EXTBUS_D31 outputs. 0
Reserved.
Description
Reserved.
Reserved.
Reserved.
Reserved.
Delay of the EMC CCLKDELAY clock.
Reserved.
Description
Delay of the EXTBUS_A0 output.
Reserved.
Delay of the EXTBUS_A1 output.
Reserved.
Delay of the EXTBUS_A2 output.
Reserved.
Delay of the EXTBUS_A3 output.
Reserved.
Delay of the EXTBUS_A4 output.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
0
-
0
-
0
-
0
Reset
value
-
-
Reset
value
-
-
-
-
0
-
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Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
Access
-
R/W
-