LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 884

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.10.4 Slave Transmitter mode
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver
(see
CON have been initialized, the I
address followed by the data direction bit which must be “1” (R) for the I
operate in the slave transmitter mode. After its own slave address and the R bit have been
received, the serial interrupt flag (SI) is set and a valid status code can be read from STAT.
This status code is used to vector to a state service routine, and the appropriate action to
be taken for each of these status codes is detailed in
mode may also be entered if arbitration is lost while the I
(see state 0xB0).
If the AA bit is reset during a transfer, the I
and enter state 0xC0 or 0xC8. The I
and will ignore the master receiver if it continues the transfer. Thus the master receiver
receives all 1s as serial data. While AA is reset, the I
slave address or a General Call address. However, the I
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the I
Figure
143). Data transfer is initialized as in the slave receiver mode. When ADR and
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
2
C block waits until it is addressed by its own slave
2
C block is switched to the not addressed slave mode
2
C block will transmit the last byte of the transfer
2
C block from the I
Chapter 37: LPC18xx I2C-bus interface
2
C block does not respond to its own
Table
2
2
C-bus is still monitored, and
C block is in the master mode
823. The slave transmitter
2
C-bus.
UM10430
© NXP B.V. 2011. All rights reserved.
2
C block to
884 of 1164