LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 30

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
3.3.4.4 EMC boot modes
The EMC boot process follows the main flow shown in
72 MHz, and a non-AES capable LPC18xx will boot directly from EMC when the image
does not contain a header. The EMC uses 8 wait states.
Note that the number of address bits selected in pin configuration is initially
EXTBUS_A[13:0]. After reading the header the address bits are extended to be in line
with the image size as defined by HASH_SIZE, e.g. if HASH_SIZE is 100 kB then pins
EXTBUS_A[16:14] are configured since 2
the image should configure extra address pins beyond the initially configured
EXTBUS_A[13:0].
Fig 12. SPIFI boot process
Fig 13. EMC boot process
SPIFI_SCK=
Setup clock
36MHz
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
EXTBUS_A[13:0]
EXTBUS_CS0
if SQI device supported
then 4-bit I/O will be used
Configuration
Setup Pin
Configuration
P3_3..P3_8
Setup Pin
17
> 100 kB. When booting without header then
see main boot flow
Read Image
address bus
see main boot flow
Image size
> 16384-16
Header
Extend
specific driver
Vendor_ID?
Vendor_ID
Vendor_ID
supported
Figure
activate
yes
Read
Chapter 3: LPC18xx Boot ROM
yes
no
13. Tthe CPU clock is set to
no
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
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