LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 250

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 170. Register overview: GPIO port (base address 0x400F 4000)
<Document ID>
User manual
Name
B0 to B31
B32 to Bx
B64 to Bx
B96 to Bx
B128 to Bx
B160 to Bx
B192 to Bx
B224 to Bx
W0 to Wx
W32 to Wx
W64 to Wx
W96 to Wx
W128 to Wx
W160 to Wx
W192 to Wx
W224 to Wx
DIR0
DIR1
DIR2
DIR3
DIR4
DIR5
DIR6
DIR7
MASK0
MASK1
MASK2
MASK3
MASK4
MASK5
MASK6
MASK7
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 169. Register overview: GPIO GROUP1 interrupt (base address 0x4008 9000)
GPIO port addresses can be read and written as bytes, halfwords, or words.
Name
PORT_ENA5
PORT_ENA6
PORT_ENA7
Address
offset
0x0000 to x001F
0x0020 to 0x003F
0x0040 to 0x005F
0x0060 to 0x007F
0x0080 to 0x009F
0x00A0 to 0x00BF
0x00C0 to0x00DF
0x00E0 to 0x00FC
0x1000 to 0x107C
0x1080 to 0x10FC
0x1100 to 0x11FC
0x1180 to 0x11FC
0x1200 to 0x12FC
0x1280 to 0x12FC
0x1300 to 0x137C
0x1380 to 0x13FC
0x2000
0x2004
0x2008
0x200C
0x2010
0x2014
0x2018
0x201C
0x2080
0x2084
0x2088
0x208C
0x2090
0x2094
0x2098
0x209C
Access Address
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
offset
0x054
0x058
0x05C
Description
Byte pin registers port 0; pins PIO0_0
to PIO0_31
Byte pin registers port 1
Byte pin registers port 2
Byte pin registers port 3
Byte pin registers port 4
Byte pin registers port 5
Byte pin registers port 6
Byte pin registers port 7
Word pin registers port 0
Word pin registers port 1
Word pin registers port 2
Word pin registers port 3
Word pin registers port 4
Word pin registers port 5
Word pin registers port 6
Word pin registers port 7
Direction registers port 0
Direction registers port 1
Direction registers port 2
Direction registers port 3
Direction registers port 4
Direction registers port 5
Direction registers port 6
Direction registers port 7
Mask register port 0
Mask register port 1
Mask register port 2
Mask register port 3
Mask register port 4
Mask register port 5
Mask register port 6
Mask register port 7
Description
GPIO grouped interrupt port 5 enable register
GPIO grouped interrupt port 5 enable register
GPIO grouped interrupt port 5 enable register
Chapter 15: LPC18xx GPIO
Reset
value
ext
ext
ext
ext
ext
ext
ext
ext
ext
ext
ext
ext
ext
ext
ext
ext
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
UM10430
Width
byte (8 bit)
byte (8 bit)
byte (8 bit)
byte (8 bit)
byte (8 bit)
byte (8 bit)
byte (8 bit)
byte (8 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
250 of 1164