LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 288

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 218. DMA request signal usage
<Document ID>
User manual
Transfer direction
Memory-to-peripheral
Memory-to-peripheral
Peripheral-to-memory
Peripheral-to-memory
Memory-to-memory
Source peripheral to destination peripheral
Source peripheral to destination peripheral
Source peripheral to destination peripheral
16.8.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow
16.8.2.2 Peripheral-to-peripheral DMA flow
Each transfer type can have either the peripheral or the DMA Controller as the flow
controller so there are eight possible control scenarios.
Table 218
For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence
occurs:
For a peripheral-to-peripheral DMA flow, the following sequence occurs:
1. Program and enable the DMA channel.
2. Wait for a DMA request.
3. The DMA Controller starts transferring data when:
4. If an error occurs while transferring the data, an error interrupt is generated and
5. Decrement the transfer count if the DMA Controller is performing the flow control.
6. If the transfer has completed (indicated by the transfer count reaching 0, if the DMA
1. Program and enable the DMA channel.
2. Wait for a source DMA request.
3. The DMA Controller starts transferring data when:
•
Peripheral-to-peripheral (master 1 only).
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
disables the DMA stream, and the flow sequence ends.
Controller is performing flow control, or by the peripheral sending a DMA request, if
the peripheral is performing flow control):
– The DMA Controller responds with a DMA acknowledge.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI,
and CCONTROL registers and go to back to step 2. However, if CLLI is 0, the DMA
stream is disabled and the flow sequence ends.
indicates the request signals used for each type of transfer.
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Request generator
Peripheral
Peripheral
Peripheral
Peripheral
DMA Controller
Source peripheral and destination peripheral
Source peripheral and destination peripheral
Source peripheral and destination peripheral
Rev. 00.13 — 20 July 2011
Flow controller
DMA Controller
Peripheral
DMA Controller
Peripheral
DMA Controller
Source peripheral
Destination peripheral
DMA Controller
UM10430
© NXP B.V. 2011. All rights reserved.
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