LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 552

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.7 LCD Control register
Table 461. Lower Panel Frame Base register (LPBASE, address 0x4000 8014) bit
The CTRL register controls the LCD operating mode and the panel pixel parameters.
Table 462. LCD Control register (CTRL, address 0x4000 8018) bit description
Bits
2:0
31:3
Bits
0
3:1
4
5
6
Symbol
-
LCDLPBASE
Symbol
LCDEN
LCDBPP
LCDBW
LCDTFT
LCDMONO8
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
LCD lower panel base address.
This is the start address of the lower panel frame data in memory
and is doubleword aligned.
Description
LCD enable control bit.
0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are low.
1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are high.
See LCD power-up and power-down sequence for details on
LCD power sequencing.
LCD bits per pixel:
Selects the number of bits per LCD pixel:
000 = 1 bpp.
001 = 2 bpp.
010 = 4 bpp.
011 = 8 bpp.
100 = 16 bpp.
101 = 24 bpp (TFT panel only).
110 = 16 bpp, 5:6:5 mode.
111 = 12 bpp, 4:4:4 mode.
STN LCD monochrome/color selection.
0 = STN LCD is color.
1 = STN LCD is monochrome.
This bit has no meaning in TFT mode.
LCD panel TFT type selection.
0 = LCD is an STN display. Use gray scaler.
1 = LCD is a TFT display. Do not use gray scaler.
Monochrome LCD interface width.
This bit controls whether a monochrome STN LCD uses a 4 or
8-bit parallel interface. It has no meaning in other modes and
must be programmed to zero.
0 = monochrome LCD uses a 4-bit interface.
1 = monochrome LCD uses a 8-bit interface.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
-
0x0
Reset
value
0x0
0x0
0x0
0x0
0x0